In a conventional multi-chip stacked package, a plurality of semiconductor chips are vertically stacked on a chip carrier with the active surfaces of the chips facing upward. Bonding wires are implemented to electrically connect the chips to the chip carrier. Comparing to back-to-back stacking, this multi-chip stacked package has the advantages of stacking more chips with better uniform bonding wire lengths connecting to different chips. However, the length of bonding wires increases when stacking more chips, the risk of wire sweeping will also increase causing most common failure mode of electrical short in this multi-chip stacked package. Film-Over-Wire (FOW) technology can be implemented to resolve wire sweeping issues by pre-encapsulating the middle sections of the bonding wires between the chips during chip stacking process to ensure no wire sweeping during molding process.
As shown in FIG. 1, a conventional multi-chip stacked package is disclosed when stacking a second chip 130 on a first chip 120. The first chip 120 is disposed on the chip carrier 110 such as printed wiring boards or lead frames. The first chip 120 has a first active surface 121 and a plurality of first bonding pads 123 disposed on a central region of the first active surface 121. The first bonding pads 123 of the first chip 120 are electrically connected to the chip carrier 110 by a plurality of bonding wires 140. The second chip 150 is provided where the second chip 150 has the same dimension as the one of the first chip 120 and has a second active surface 151 and a plurality of second bonding pads 153 disposed on a central region of the second active surface 151. Before stacking the second chip 150 on top of the first active surface 121 of the first chip 120, a wafer-level die-attaching material 130 (FOW film) is pre-formed on the second back surface 152 of the second chip 150 to attach the second chip 150 to the first chip 120 where the wafer-level die-attaching material 130 is partially cured paste, i.e., B-stage paste, to partially encapsulate the bonding wires 140.
As shown in FIG. 2, the die-attaching material 130 is attached to the first active surface 121 of the first chip 120 by a pre-decided pressure and all of the bonding wires 140 are partially encapsulated during stacking of the second chip 150. However, the bonding wires 140 are collapsed and deformed under the die-bonding pressure from the die-attaching material 130 to directly contact with the first active surface 121 of the first chip 120 leading to poor packaging quality, more the worse, leading to electrical short between the adjacent bonding wires 140 and air gap between the chips 120 and 150 causing lower packaging yield. Therefore, even with the existing wire bonding technology, a wire capillary (wire-bonding tool) can move in various bonding directions and track with multiple bending angles to increase the horizontal sections of the bonding wires 140 suspended above the first chip 120 (as shown in FIG. 1), however, the collapse and deformation of the bonding wires 140 during attaching the second chip 150 can not be avoided. Furthermore, another method to improve collapse and deformation of bonding wires 140 during stacking process is to change the physical properties of the die-attaching material 130 to be softer and more fluid-like, however, the volatile materials in the die-attaching material 130 can not be exhausted leading to trapped bubbles in the die-attaching material 130. Moreover, uniformity of curing level of the die-attaching material 130 becomes an issue, i.e., curing level at the peripheries of the die-attaching material 130 is higher than the one at the center. Once the peripheries of the die-attaching material 130 is fully cured, then the volatile materials at the center of the die-attaching material 130 will be blocked and can not be exhausted. Even with the extended curing time, the center of the die-attaching material 130 still can not be fully cured leading to chip peeling issues due to uneven uniformity of curing level.
In Taiwan Patent No. 1250597, entitled “Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips”, Lin et al. disclose a method to avoid bonding wires from collapse and deformation from directly contacting with the active surface of the bottom chip. A patterned bottom die-attaching layer is pre-formed on the active surface of the bottom chip and a top die-attaching layer is pre-formed on the back surface of the top chip. Then the top chip is pressed downward to attach to the bottom chip so that portions of the bonding wires above the active surface of the bottom chip are encapsulated between the top and bottom die-attaching layers. However, the pattern of the top die-attaching layer is different from the one of the bottom die-attaching layer, therefore, the top die-attaching layer can not easily fill the central gap of the bottom die-attaching layer causing trapped bubbles leading to package reliability issues. Furthermore, since the top die-attaching layer has to be pre-formed on the back surface of the top chip, extra components and process are needed where the height of the stacked package is also increased which can not meet the light, slim, thin, and small requirements of electronic products with lower cost. Moreover, trapped bubbles in the die-attaching layer will become an issue.
In U.S. Pat. No. 6,683,385 B2, entitled “LOW PROFILE STACK SEMICONDUCTOR PACKAGE”, Tsai et al. disclose another method to avoid bonding wires collapse and deformation from directly contact with the active surface of the bottom chip. An insulating cushion member is disposed at peripheral edges of the active surface of the bottom chip. When the bonding wires extend from the bonding pads of the bottom chip and turn downward to the substrate by overpassing the cushion member, the bonding wires are approximately horizontal and in contact with the cushion member to avoid directly contact with the peripheral edge. Then, a die-attaching layer is disposed on the bottom chip with the top chip stacked on top of the die-attaching layer of the bottom chip so that the electrical connection mechanism of the bottom chip will not be damaged nor affected. However, for the disclosed method, another cushion member is needed leading to more complicated process with higher cost where the cushion member located at the peripheries of the chip will also hinder the exhaust of the volatile materials inside the die-attaching layer.